\doxysection{DBGMCU\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_b_g_m_c_u___type_def}{}\label{struct_d_b_g_m_c_u___type_def}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}


Debug MCU.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a0cc3561c124d06bb57dfa855e43ed99f}{IDCODE}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a15981828f2b915d38570cf6684e99a53}{CR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_af30b2b29d8a114933db69ce77f6bb8f3}{RESERVED4}} \mbox{[}11\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a49a2f06534a2aa7c963e33fb819ed717}{APB3\+FZ1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a12d302a1277fe4f4c5efecb996a70707}{RESERVED5}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_ade78d6c1b3af2409a6b3a7f7ccc62db3}{APB1\+LFZ1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_ae4670d84a9e3cde5490e47781665c9fc}{RESERVED6}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_aec754f328723263fec5e157d06720128}{APB1\+HFZ1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a39b1f573d3b83ad5d6a18e5a632fb530}{RESERVED7}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a1da46d5c89c571f80d2976cd3cabaa52}{APB2\+FZ1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_ade14a892a72d72b9414be3de6ad38982}{RESERVED8}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a11a649a39dcd7c14e9d08c02fdf23188}{APB4\+FZ1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a0a70e168bb032f762787ee8c419aae4f}{RESERVED9}} \mbox{[}990\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a0b0b1c1be440af57d3bf196703745cbf}{PIDR4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_afc0bdc356fcf3977d8f53b063155e41b}{RESERVED10}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_aedbef06ecb7be4c8924830b0dfe80524}{PIDR0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_aa9b45376515ccd8f0b1849c52ef9c11d}{PIDR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a880d3a2e95aa53ef8f16e34db183d4f7}{PIDR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_af167e600bc8005e14aeb850fa2be7780}{PIDR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a4251fb34556fa52aaded20acdfa3c09e}{CIDR0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a929f2d4e6fa1f7d8acf7a85f60d729aa}{CIDR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_a899def83ae7e50fd889b0ff3a7200b87}{CIDR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def_aa0c05391c70942f7b6d70d9a7669fff1}{CIDR3}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Debug MCU. 

\label{doc-variable-members}
\Hypertarget{struct_d_b_g_m_c_u___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_b_g_m_c_u___type_def_aec754f328723263fec5e157d06720128}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!APB1HFZ1@{APB1HFZ1}}
\index{APB1HFZ1@{APB1HFZ1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1HFZ1}{APB1HFZ1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_aec754f328723263fec5e157d06720128} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+APB1\+HFZ1}

Debug MCU APB1\+LFZ1 freeze register, Address offset\+: 0x44 \Hypertarget{struct_d_b_g_m_c_u___type_def_ade78d6c1b3af2409a6b3a7f7ccc62db3}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!APB1LFZ1@{APB1LFZ1}}
\index{APB1LFZ1@{APB1LFZ1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1LFZ1}{APB1LFZ1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_ade78d6c1b3af2409a6b3a7f7ccc62db3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+APB1\+LFZ1}

Debug MCU APB1\+LFZ1 freeze register, Address offset\+: 0x3C \Hypertarget{struct_d_b_g_m_c_u___type_def_a1da46d5c89c571f80d2976cd3cabaa52}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!APB2FZ1@{APB2FZ1}}
\index{APB2FZ1@{APB2FZ1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB2FZ1}{APB2FZ1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a1da46d5c89c571f80d2976cd3cabaa52} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+APB2\+FZ1}

Debug MCU APB2\+FZ1 freeze register, Address offset\+: 0x4C \Hypertarget{struct_d_b_g_m_c_u___type_def_a49a2f06534a2aa7c963e33fb819ed717}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!APB3FZ1@{APB3FZ1}}
\index{APB3FZ1@{APB3FZ1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB3FZ1}{APB3FZ1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a49a2f06534a2aa7c963e33fb819ed717} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+APB3\+FZ1}

Debug MCU APB3\+FZ1 freeze register, Address offset\+: 0x34 \Hypertarget{struct_d_b_g_m_c_u___type_def_a11a649a39dcd7c14e9d08c02fdf23188}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!APB4FZ1@{APB4FZ1}}
\index{APB4FZ1@{APB4FZ1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB4FZ1}{APB4FZ1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a11a649a39dcd7c14e9d08c02fdf23188} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+APB4\+FZ1}

Debug MCU APB4\+FZ1 freeze register, Address offset\+: 0x54 \Hypertarget{struct_d_b_g_m_c_u___type_def_a4251fb34556fa52aaded20acdfa3c09e}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!CIDR0@{CIDR0}}
\index{CIDR0@{CIDR0}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIDR0}{CIDR0}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a4251fb34556fa52aaded20acdfa3c09e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+CIDR0}

Debug MCU component identity register 0, Address offset\+: 0x\+FF0 \Hypertarget{struct_d_b_g_m_c_u___type_def_a929f2d4e6fa1f7d8acf7a85f60d729aa}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!CIDR1@{CIDR1}}
\index{CIDR1@{CIDR1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIDR1}{CIDR1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a929f2d4e6fa1f7d8acf7a85f60d729aa} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+CIDR1}

Debug MCU component identity register 1, Address offset\+: 0x\+FF4 \Hypertarget{struct_d_b_g_m_c_u___type_def_a899def83ae7e50fd889b0ff3a7200b87}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!CIDR2@{CIDR2}}
\index{CIDR2@{CIDR2}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIDR2}{CIDR2}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a899def83ae7e50fd889b0ff3a7200b87} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+CIDR2}

Debug MCU component identity register 2, Address offset\+: 0x\+FF8 \Hypertarget{struct_d_b_g_m_c_u___type_def_aa0c05391c70942f7b6d70d9a7669fff1}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!CIDR3@{CIDR3}}
\index{CIDR3@{CIDR3}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIDR3}{CIDR3}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_aa0c05391c70942f7b6d70d9a7669fff1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+CIDR3}

Debug MCU component identity register 3, Address offset\+: 0x\+FFC \Hypertarget{struct_d_b_g_m_c_u___type_def_a15981828f2b915d38570cf6684e99a53}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!CR@{CR}}
\index{CR@{CR}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a15981828f2b915d38570cf6684e99a53} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+CR}

Debug MCU configuration register, Address offset\+: 0x04 \Hypertarget{struct_d_b_g_m_c_u___type_def_a0cc3561c124d06bb57dfa855e43ed99f}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!IDCODE@{IDCODE}}
\index{IDCODE@{IDCODE}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDCODE}{IDCODE}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a0cc3561c124d06bb57dfa855e43ed99f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+IDCODE}

MCU device ID code, Address offset\+: 0x00 \Hypertarget{struct_d_b_g_m_c_u___type_def_aedbef06ecb7be4c8924830b0dfe80524}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!PIDR0@{PIDR0}}
\index{PIDR0@{PIDR0}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIDR0}{PIDR0}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_aedbef06ecb7be4c8924830b0dfe80524} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+PIDR0}

Debug MCU peripheral identity register 0, Address offset\+: 0x\+FE0 \Hypertarget{struct_d_b_g_m_c_u___type_def_aa9b45376515ccd8f0b1849c52ef9c11d}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!PIDR1@{PIDR1}}
\index{PIDR1@{PIDR1}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIDR1}{PIDR1}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_aa9b45376515ccd8f0b1849c52ef9c11d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+PIDR1}

Debug MCU peripheral identity register 1, Address offset\+: 0x\+FE4 \Hypertarget{struct_d_b_g_m_c_u___type_def_a880d3a2e95aa53ef8f16e34db183d4f7}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!PIDR2@{PIDR2}}
\index{PIDR2@{PIDR2}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIDR2}{PIDR2}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a880d3a2e95aa53ef8f16e34db183d4f7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+PIDR2}

Debug MCU peripheral identity register 2, Address offset\+: 0x\+FE8 \Hypertarget{struct_d_b_g_m_c_u___type_def_af167e600bc8005e14aeb850fa2be7780}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!PIDR3@{PIDR3}}
\index{PIDR3@{PIDR3}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIDR3}{PIDR3}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_af167e600bc8005e14aeb850fa2be7780} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+PIDR3}

Debug MCU peripheral identity register 3, Address offset\+: 0x\+FEC \Hypertarget{struct_d_b_g_m_c_u___type_def_a0b0b1c1be440af57d3bf196703745cbf}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!PIDR4@{PIDR4}}
\index{PIDR4@{PIDR4}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIDR4}{PIDR4}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a0b0b1c1be440af57d3bf196703745cbf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+PIDR4}

Debug MCU peripheral identity register 4, Address offset\+: 0x\+FD0 \Hypertarget{struct_d_b_g_m_c_u___type_def_afc0bdc356fcf3977d8f53b063155e41b}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED10@{RESERVED10}}
\index{RESERVED10@{RESERVED10}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED10}{RESERVED10}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_afc0bdc356fcf3977d8f53b063155e41b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED10\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x\+FD4-\/0x\+FDC \Hypertarget{struct_d_b_g_m_c_u___type_def_af30b2b29d8a114933db69ce77f6bb8f3}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED4@{RESERVED4}}
\index{RESERVED4@{RESERVED4}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED4}{RESERVED4}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_af30b2b29d8a114933db69ce77f6bb8f3} 
uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED4\mbox{[}11\mbox{]}}

Reserved, Address offset\+: 0x08 \Hypertarget{struct_d_b_g_m_c_u___type_def_a12d302a1277fe4f4c5efecb996a70707}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED5@{RESERVED5}}
\index{RESERVED5@{RESERVED5}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED5}{RESERVED5}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a12d302a1277fe4f4c5efecb996a70707} 
uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED5}

Reserved, Address offset\+: 0x38 \Hypertarget{struct_d_b_g_m_c_u___type_def_ae4670d84a9e3cde5490e47781665c9fc}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED6@{RESERVED6}}
\index{RESERVED6@{RESERVED6}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED6}{RESERVED6}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_ae4670d84a9e3cde5490e47781665c9fc} 
uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED6}

Reserved, Address offset\+: 0x40 \Hypertarget{struct_d_b_g_m_c_u___type_def_a39b1f573d3b83ad5d6a18e5a632fb530}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED7@{RESERVED7}}
\index{RESERVED7@{RESERVED7}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED7}{RESERVED7}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a39b1f573d3b83ad5d6a18e5a632fb530} 
uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED7}

Reserved, Address offset\+: 0x48 \Hypertarget{struct_d_b_g_m_c_u___type_def_ade14a892a72d72b9414be3de6ad38982}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED8@{RESERVED8}}
\index{RESERVED8@{RESERVED8}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED8}{RESERVED8}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_ade14a892a72d72b9414be3de6ad38982} 
uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED8}

Reserved, Address offset\+: 0x50 \Hypertarget{struct_d_b_g_m_c_u___type_def_a0a70e168bb032f762787ee8c419aae4f}\index{DBGMCU\_TypeDef@{DBGMCU\_TypeDef}!RESERVED9@{RESERVED9}}
\index{RESERVED9@{RESERVED9}!DBGMCU\_TypeDef@{DBGMCU\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED9}{RESERVED9}}
{\footnotesize\ttfamily \label{struct_d_b_g_m_c_u___type_def_a0a70e168bb032f762787ee8c419aae4f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DBGMCU\+\_\+\+Type\+Def\+::\+RESERVED9\mbox{[}990\mbox{]}}

Reserved, Address offset\+: 0x58-\/0x\+FCC 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
